Semiconductor chips are used in all kinds of electronic and other devices and are well-known. Today's wide-spread use of such chips, and consumer demands for more powerful and more compact devices dictates that chip manufacturers continuously decrease the physical size and continuously increase the functionality of such chips. To shrink the chip footprint, manufacturers increasingly push to obtain smaller feature sizes and die sizes, resulting in a larger number of dies within a fixed wafer size. To shrink the height of the chips, manufacturers strive to create three-dimensional or stacked integrated circuits (3DIC's). Existing manufacturing methods for these stacked chips may be time consuming, such as the pick-and-place methods used to bond individual chips to other chips or to wafers. The higher the density of the dies in a given wafer size, the longer time such a bonding process consumes, which reduces the manufacturing output measured in wafers bonded per hour. Next generation fabrication methods are envisioned to integrate type III-V devices to Complementary Metal Oxide Semiconductor (CMOS) chips or to wafers, and to do so in a high reliability, high speed and footprint efficient manner.